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... Hrishikesh M Member since: 12 Mei 2007 Total points: 102 (Level 1) Add to My Contacts; Block User
Dr. Hrishikesh M P: M.Com, M.Phil: Sundar Raj Vijayanagar: B.E, M.Tech Abhijit Roy: BE, MBA: U V Mohan: BE, M.Tech: S.G.Shivashankar: BE, ME. USHA SHANKAR: M.COM , M. Phil
\REF{[4]} Hrishikesh M S \it et al. \rm The optimal logic depth per pipeline stage is 6 to 8 FO$_4$ inverter delays. In {\it Proc. the 29th ISCA}, IEEE CS Press ...
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INECO (Construction industry): Planning Engineer, (March 2005-April 2007)