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Robust LSI Architecture and its High Speed Viterbi Decoder: Author(s) * Yasuyuki Hatakawa, Yoshikazu Miyanaga(Hokkaido Univ.) Page(s) pp. II-577 - II-580
Author(s) * Yasuyuki Hatakawa, Yoshikazu Miyanaga(Graduate School of Information Science and Technology, Hokkaido University) Page(s) pp. II-577 - II-580
Noriaki MIYAZAKI, Yasuyuki HATAKAWA and Toshinori SUZUKI: 2209-2217: Development of 100 MHz Bandwidth Testbed toward IMT-Advanced and Experimental Results Including Rotational OFDM and ...
... 11:10 - 11:50"A LSI Design of a High-Speed Wireless Communication System using Dynamic Reconfigurable Architecture" Yoshikazu Miyanaga, Kentarou Yoshikawa and Yasuyuki Hatakawa ...
Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi (KDDI R&D Labs.), Nandar Lynn : SR, AN, USN (Joint) 2009-10-23 11:00: Miyagi: Tohoku Univ. Performance of Cooperative HARQ with Relay ...
Robust LSI Architecture and its High Speed Viterbi Decoder: Author(s) * Yasuyuki Hatakawa, Yoshikazu Miyanaga(Hokkaido Univ.) Page(s) pp. II-577 - II-580
Author(s) * Yasuyuki Hatakawa, Yoshikazu Miyanaga(Graduate School of Information Science and Technology, Hokkaido University) Page(s) pp. II-577 - II-580
Noriaki MIYAZAKI, Yasuyuki HATAKAWA and Toshinori SUZUKI: 2209-2217: Development of 100 MHz Bandwidth Testbed toward IMT-Advanced and Experimental Results Including ...
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